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a preliminary technical data blackfin and the blackfi n logo are registered tradem arks of analog devices, inc. blackfin ? embedded symmetric multi-processor adsp-bf561 rev. prc information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o.box 9106, norwood, ma 02062-9106 u.s.a. tel:781/329-4700 www.analog.com fax:781/326-8703 ? 2004 analog devices, inc. all rights reserved. features dual symmetric 600 mhz high performance blackfin core 328 kbytes of on-chip memory (see memory info on page 3 ) each blackfin core includes: two 16-bit macs, two 40-bit alus, four 8-bit video alus, 40-bit shifter risc-like register and instruction model for ease of pro- gramming and compiler-friendly support advanced debug, trace, an d performance- monitoring 0.8 - 1.2v core v dd with on-chip voltage regulation 3.3v and 2.5v tolerant i/o 256-ball mini bga and 297-ball pbga package options peripherals two parallel input/output peripheral interface units sup- porting itu-r 656 video and glueless interface to adi analog front end adcs two dual channel, full duplex synchronous serial ports sup- porting eight stereo i 2 s channels dual 16 channel dma controllers and one internal memory dma controller 12 general purpose 32-bit timer/counters, with pwm capability spi-compatible port uart with support for irda? dual watchdog timers 48 programable flags on-chip phase locked loop capable of 1x to 63x frequency multiplication figure 1. function al block diagram dma external port flash/sdram control 32 16 32 16 boot rom pab eab dab dab ppi ppi voltage regulator jtag test emulation gpio spi uart irda? sport0 timers sport1 imdma controller l1 instruction memory l1 data memory mmu b l2 sram 128 kbytes core system / bus interface l1 instruction memory l1 data memory mmu b irq ctrl/ timer irq ctrl/ timer controller2 dma controller1
rev. prc | page 2 of 52 | april 2004 adsp-bf561 preliminary technical data table of contents general description ................................................. 3 portable low-power architecture ............................. 3 blackfin processor core .......................................... 3 memory architecture ............................................ 4 internal (on-chip) memory ................................. 4 external (off-chip) memory ................................ 5 i/o memory space ............................................. 6 booting ........................................................... 6 event handling ................................................. 6 core event controller (cec) ................................ 6 system interrupt controller (sic) .......................... 6 event control ................................................... 7 dma controllers .................................................. 8 watchdog timers ................................................ 8 serial ports (sports) ............................................ 9 serial peripheral interface (spi) ports ........................ 9 uart port .......................................................... 9 programmable flags (pfx) .................................... 10 timers ............................................................. 10 parallel peripheral interface ................................... 10 general purpose mode descriptions .................... 10 input mode .................................................... 10 itu -r 656 mode descriptions ........................... 10 active video only mode ................................... 10 vertical blanking interval mode .......................... 11 entire field mode ............................................ 11 dynamic power management ................................ 11 full-on operating mode C maximum performance . 11 active operating mode C moderate power savings .. 11 hibernate operating modemaximum static power savings ....................................................... 11 sleep operating mode C high power savings ......... 11 deep sleep operating mode C max. power savings .. 11 power savings ................................................. 12 voltage regulation .............................................. 12 clock signals ..................................................... 13 booting modes ................................................... 13 instruction set description ................................... 14 development tools .............................................. 14 designing an emulator-compatible processor board (target) ................................... 15 additional information ........................................ 15 pin descriptions .................................................... 16 specifications ........................................................ 20 recommended operating conditions ...................... 20 electrical characteristics ....................................... 20 absolute maximum ratings ................................... 21 esd sensitivity ................................................... 21 timing specifications ........................................... 22 clock and reset timing ..................................... 23 asynchronous memory read cycle timing ............ 24 asynchronous memory write cycle timing ........... 25 sdram interface timing .................................. 26 external port bus request and grant cycle timing .. 27 parallel peripheral interface timing ..................... 28 serial ports ..................................................... 29 serial peripheral interface (spi) portmaster timing 34 serial peripheral interface (spi) portslave timing . 36 universal asynchronous rece iver-transmitter (uart) portreceive and transmit timing .................. 38 timer cycle timing .......................................... 39 programmable flags cycle timing ....................... 40 jtag test and emulation port timing ................. 41 power dissipation ............................................... 42 output drive currents ......................................... 42 test conditions .................................................. 42 output enable time ......................................... 43 output disable time ......................................... 43 example system hold time calculation ................... 43 capacitive loading .............................................. 44 256-ball mbga pin configurations ... ......................... 45 297-ball pbga pin configurations ............................. 47 outline dimensions ................................................ 50 outline dimensions ................................................ 51 ordering guide ..................................................... 51 revision history revision prc: ? edits made to pinlists and timing specification.
adsp-bf561 preliminary technical data rev. prc | page 3 of 52 | april 2004 general description the adsp-bf561 processor is a high-performance member of the blackfin family of products targeting a variety of multimedia and telecommunications applications. at the heart of this device are two independent analog devices blackfin processors. these blackfin processors combine a dual-mac state-of-the-art signal processing engine, the advantage of a clean, orthogonal risc- like microprocessor instruction se t, and single-instruction, mul- tiple-data (simd) multimedia capabilities into a single instruction-set architecture. th e adsp-bf561 device integrates a general purpose set of digital imaging peripherals creating a complete system on-chip solution for digital imaging and multi- media applications. the adsp-bf561 processor ha s 328 kbytes of on-chip mem- ory. each blackfin core includes: ? 16k bytes of instruction sram/cache ? 16k bytes of instruction sram ? 32k bytes of data sram/cache ? 32k bytes of data sram ? 4k bytes of scratchpad sram additional on-chip memo ry peripherals include: ? 128 kbytes of low latency on-chip sram ? four channel internal memory dma controller ? external memory controller with glueless support for sdram, sram, and flash portable low-power architecture blackfin processors provide world-class power management and performance for embedded signal processing applications. blackfin processors are designed in a low power and low voltage design methodology and feature dynamic power management. dynamic power management is the ability to vary both the volt- age and frequency of operation to significantly lo wer the overall power dissipation. this translates into an exponential reduction in power dissipation providing lo nger battery life to portable applications. blackfin processor core as shown in figure 2 , each blackfin core contains two multi- plier/accumulators (macs), two 40-bit alus, four video alus, and a single shifter. the comput ational units process 8-bit, 16- bit, or 32-bit data from the register file. figure 2. blackfin processor core sp se quencer align decode loop buffer dag0 dag1 16 16 8 8 8 8 40 40 a0 a1 barrel shifter data arithmetic unit control unit address arithmetic unit fp p5 p4 p3 p2 p1 p0 r7 r6 r5 r4 r3 r2 r1 r0 i3 i2 i1 i0 l3 l2 l1 l0 b3 b2 b1 b0 m3 m2 m1 m0
rev. prc | page 4 of 52 | april 2004 adsp-bf561 preliminary technical data each mac performs a 16-bit by 16 -bit multiply in every cycle, with an accumulation to a 40-bit result, providing 8 bits of extended precision. the alus perform a standard set of arith- metic and logical operations. with two alus capable of operating on 16- or 32-bit data, the flexibility of the computa- tion units covers the signal proc essing requirements of a varied set of application needs. each of the two 32-bit input registers can be regarded as two 16- bit halves, so each alu can acco mplish very flexible single 16- bit arithmetic operations. by viewing the registers as pairs of 16- bit operands, dual 16-bit or single 32-bit operations can be accomplished in a single cycle. by further taking advantage of the second alu, quad 16-bit op erations can be accomplished simply, accelerating th e per cycle throughput. the powerful 40-bit shifter has extensive capabilities for per- forming shifting, rotating, normalization, extraction, and depositing of data. the data for the computational units is found in a multi-ported register file of sixteen 16-bit entries or eight 32-bit entries. a powerful program sequencer controls the flow of instruction execution, including instruction alignment and decoding. the sequencer supports conditional ju mps and subroutine calls, as well as zero-overhead looping. a lo op buffer stores instructions locally, eliminating instructio n memory accesses for tight looped code. two data address generators (dags) provide addresses for simultaneous dual operand fetches from memory. the dags share a register file containing four sets of 32-bit index, modify, length, and base registers. eigh t additional 32-bit registers pro- vide pointers for general inde xing of variables and stack locations. blackfin processors support a modified harvard architecture in combination with a hierarchical memory structure. level 1 (l1) memories are those that typically operate at the full processor speed with little or no latency. level 2 (l2) memories are other memories, on-chip or off-chip, that may take multiple processor cycles to access. at the l1 leve l, the instruction memory holds instructions only. the two data memories hold data, and a dedi- cated scratchpad data memory stores stack and local variable information. at the l2 level, th ere is a single unified memory space, holding both instructions and data. in addition, half of l1 instruct ion memory and half of l1 data memories may be configured as either static rams (srams) or caches. the memory management unit (mmu) provides mem- ory protection for individual task s that may be operating on the core and may protect system re gisters from unintended access. the architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. user mode has restricted access to certain syst em resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the sy stem and core resources. the blackfin instruction set has been optimized so that 16-bit op-codes represent the most frequently used instructions, resulting in excellent compiled code density. complex dsp instructions are encoded into 32- bit op-codes, representing fully featured multifunctio n instructions. blackfin processors sup- port a limited multi-issue capabi lity, where a 32-bit instruction can be issued in parallel with tw o 16-bit instructions, allowing the programmer to use many of the core resources in a single instruction cycle. the blackfin assembly language uses an algebraic syntax for ease of coding and readability. the architecture has been opti- mized for use in conjunction with the visualdsp c/c++ compiler, resulting in fast and efficient software implementations. memory architecture the adsp-bf561 views memory as a single unified 4g-byte address space, using 32-bit addr esses. all resources including internal memory, external memo ry, and i/o control registers occupy separate sections of th is common address space. the memory portions of this address space are arranged in a hierar- chical structure to provide a go od cost/performance balance of some very fast, low-latency memory as cache or sram very close to the processor, and larg er, lower-cost and performance- memory systems farthe r away from the processor. the adsp- bf561 memory map is shown in figure 3 . the l1 memory system in each core is the high est-performance memory available to each blackfin core. the l2 memory pro- vides additional capa city with lower performance. lastly, the off-chip memory system, acce ssed through the external bus interface unit (ebiu), provides expansion with sdram, flash memory, and sram, optionally accessing more than 768m bytes of physical memory. the memory dma controllers pro- vide high-bandwidth data-movement capability. they can perform block transfers of code or data between the internal l1/l2 memories and the external memory spaces. internal (on-chip) memory the adsp-bf561 has four blocks of on-chip memory providing high-bandwidth access to the core. the first is the l1 instruction memory of each blackfin core consisting of 16k bytes of 4-wa y set-associativ e cache memory and 16k bytes of sram. the cach e memory may also be config- ured as an sram. this memory is accessed at full processor speed. when configured as sram, each of the two 16k banks of memory is broken into 4k sub-banks which can be indepen- dently accessed by the processor and dma. the second on-chip memory block is the l1 data memory of each blackfin core which consis ts of four banks of 16k bytes each. two of the l1 data memory banks can be configured as one way of a two-way set associat ive cache or as an sram. the other two banks are configured as sram. all banks are accessed at full processor speed. when co nfigured as sram, each of the four 16k banks of memory is br oken into 4k sub-banks which can be independently accessed by the processor and dma. the third memory block associated with each core is a 4k-byte scratchpad sram which runs at the same speed as the l1 mem- ories, but is only accessible as data sram (it cannot be configured as cache memory an d is not accessible via dma).
adsp-bf561 preliminary technical data rev. prc | page 5 of 52 | april 2004 the fourth on-chip memory syst em is the l2 sram memory array which provides 128k bytes of high speed sram operating at one half the bandwidth of the core, and slightly longer latency than the l1 memory banks. the l2 memory is a unified instruc- tion and data memory and can hold any mixture of code and data required by the system de sign. the blackfin cores share a dedicated low-latency 64-bit wide data path port into the l2 sram memory. each blackfin core processor ha s its own set of core memory mapped registers (mmrs) but share the same system mmr registers and 128 kb l2 sram memory. external (off-chip) memory the adsp-bf561 external memory is accessed via the external bus interface unit (ebiu). this interface provides a glueless connection to up to four banks of synchronous dram (sdram) as well as up to four banks of asynchronous memory devices including flash, epro m, rom, sram, and memory mapped i/o devices. the pc133-compliant sdram cont roller can be programmed to interface to up to four banks of sdram, with each bank con- taining between 16m bytes and 128m bytes providing access to up to 512m bytes of sdram. ea ch bank is independently pro- grammable and is contiguous with adjacent banks regardless of the sizes of the differe nt banks or their placement. this allows flexible configuration and upgradability of system memory while allowing the core to view all sdram as a single, contigu- ous, physical address space. the asynchronous memory cont roller can also be programmed to control up to four banks of de vices with very flexible timing parameters for a wide variety of devices. each bank occupies a figure 3. memory map reserved async memory bank 3 async memory bank 2 async memory bank 1 async memory bank 0 0xff80 0000 0xff70 1000 0xff70 0000 0xff61 4000 0xff50 4000 0xff50 0000 0xff40 8000 0xff40 4000 0xff61 0000 0xff60 4000 0xff60 0000 0xff50 8000 0xff40 0000 l1 scratchpad sram (4k) l1 i nstructi on sram/ cache ( 16k) l1 i nstructi on sram (16k) l1 data bank b sram/ cache ( 16k) l1 data bank b sram (16k) l1 data bank a sram/ cache ( 16k) l1 data bank a sram (16k) c o r e a m e m o r ym a p c o r e b m e m o r ym a p core mmr regi sters core mmr regi sters system mmr registers l1 scratchpad sram ( 4k) reserved l1 i nstruction sram/cache ( 16k) l1 i nstructi on sram ( 16k) l1 data bank b sram/ cache (16k) l1 data bank b sram (16k) l1 data bank a sram/ cache (16k) l1 data bank a sram (16k) l2 sram (128k) boot rom sdram bank 3 sdram bank 2 sdram bank 1 sdram bank 0 0xffe0 0000 0xffc0 0000 0xffb0 1000 0xffb0 0000 0xffa1 4000 0xffa1 0000 0xffa0 4000 0xffa0 0000 0xff90 8000 0xff90 4000 0xff90 0000 0xff80 8000 0xff80 4000 0xfeb2 0000 0xfeb0 0000 0xef00 4000 0xef00 0000 0x3000 0000 0x2c00 0000 0x2800 0000 0x2400 0000 0x2000 0000 0x0000 0000 reserved i nternal memory external memory 0xffff ffff topoflastsdrampage reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved 0xff80 0000
rev. prc | page 6 of 52 | april 2004 adsp-bf561 preliminary technical data 64m-byte segment regardless of the size of the devices used so that these banks will only be cont iguous if fully populated with 64m bytes of memory. i/o memory space blackfin processors do not defi ne a separate i/o space. all resources are mapped through the fl at 32-bit address space. on- chip i/o devices have their cont rol registers mapped into mem- ory-mapped registers (mmrs) at addresses near the top of the 4g-byte address space. these ar e separated into two smaller blocks, one which contains the control mmrs for all core func- tions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. the core mmrs are accessible only by the core and only in supervisor mode and appear as reserved space by on-chip peripherals. the system mmrs ar e accessible by the core in supervisor mode and can be mapped as either visible or reserved to other devices, depending on the system pr otection model desired. booting the adsp-bf561 contains a small boot kernel, which config- ures the appropriate peripheral for booting. if the adsp-bf561 is configured to boot from bo ot rom memory space, the pro- cessor starts executing from the on-chip boot rom. event handling the event controller on the adsp -bf561 handles all asynchro- nous and synchronous events to the processor. the adsp- bf561 provides event handling th at supports both nesting and prioritization. nesting allows multiple event service routines to be active simultaneously. prioriti zation ensures that servicing of a higher-priority event takes precedence over servicing of a lower-priority event. the contro ller provides support for five different types of events: ? emulation C an emulation ev ent causes the processor to enter emulation mode, allowing command and control of the processor via the jtag interface. ? reset C this event resets the processor. ? non-maskable interrupt (nmi) C the nmi event can be generated by the software watchdog timer or by the nmi input signal to the processor. the nmi event is frequently used as a power-down indicator to initiate an orderly shut down of the system. ? exceptions C events that occur synchronously to program flow, i.e., the exception will be taken before the instruction is allowed to complete. conditions such as data alignment violations, undefined instructions, etc. cause exceptions. ? interrupts C events that occur asynchronously to program flow. they are caused by time rs, peripherals, input pins, and an explicit software instruction. each event has an associated regi ster to hold the return address and an associated return-from- event instruction. when an event is triggered, the state of the processor is saved on the supervisor stack. the adsp-bf561 event controller consists of two stages, the core event controller (cec) and the system interrupt control- ler (sic). the core event cont roller works with the system interrupt controller to prioritize and control all system events. conceptually, interrupts from the peripherals enter into the sic, and are then routed directly into the general-purpose inter- rupts of the cec. core event controller (cec) the cec supports nine general-purpose interrupts (ivg15C7), in addition to the dedicated interrupt and exception events. of these general-purpose interrupts, the two lowest-priority inter- rupts (ivg15C14) are recommended to be reserved for software interrupt handlers, leaving seven prioritized interrupt inputs to support the peripherals of the adsp-bf561. table 1 describes the inputs to the cec, identifies their names in the event vector table (evt), and lists their priorities. system interrupt controller (sic) the system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources, to the prioritized general-purpose interrupt inputs of the cec. although the adsp-bf561 provides a default mapping, the user can alter the mappings and priorities of interrupt events by writ- ing the appropriate values into the interrupt assignment registers (iar). table 2 describes the inputs into the sic and the default mappings into the cec. table 1. core event controller (cec) priority (0 is highest) event class evt entry 0emulation/test emu 1reset rst 2 non-maskable nmi 3exceptions evx 4 global enable - 5 hardware error ivhw 6core timer ivtmr 7 general interrupt 7 ivg7 8 general interrupt 8 ivg8 9 general interrupt 9 ivg9 10 general interrupt 10 ivg10 11 general interrupt 11 ivg11 12 general interrupt 12 ivg12 13 general interrupt 13 ivg13 14 general interrupt 14 ivg14 15 general interrupt 15 ivg15
adsp-bf561 preliminary technical data rev. prc | page 7 of 52 | april 2004 event control the adsp-bf561 provides the user with a very flexible mecha- nism to control the processing of events. in the cec, three registers are used to coordinate and control events . each of the registers, as follows, is 16-bits wide, while each bit represents a particular event class: ? cec interrupt latch register (ilat) C the ilat register indicates when events have been latched. the appropriate bit is set when the processo r has latched the event and cleared when the even t has been accepted into the system. this register is updated automatically by the controller, but may be written only when its corresponding imask bit is cleared. ? cec interrupt mask regist er (imask) C the imask reg- ister controls the masking and unmasking of individual events. when a bit is set in the imask register, that event is unmasked and will be processe d by the cec when asserted. a cleared bit in the imask register masks the event thereby preventing the proce ssor from servicing the event even though the event may be latched in the ilat register. this register may be read from or written to while in super- visor mode. (note that general-purpose interrupts can be globally enabled and disabled with the sti and cli instruc- tions, respectively.) ? cec interrupt pending register (ipend) C the ipend register keeps track of all ne sted events. a set bit in the ipend register indicates the event is currently active or nested at some level. this re gister is updated automatically by the controller but may be read while in supervisor mode. table 2. peripheral interrupt source reset state peripheral interrupt source chan 1 ivg 2 pll wakeup 0 ivg07 dma1 error 1 ivg07 dma2 error 2 ivg07 imdma error 3 ivg07 ppi1 error 4 ivg07 ppi2 error 5 ivg07 sport0 error 6 ivg07 sport1 error 7 ivg07 spi error 8 ivg07 uart error 9 ivg07 reserved 10 ivg07 dma1 0 interrupt 11 ivg08 dma1 1 interrupt 12 ivg08 dma1 2 interrupt 13 ivg08 dma1 3 interrupt 14 ivg08 dma1 4 interrupt 15 ivg08 dma1 5 interrupt 16 ivg08 dma1 6 interrupt 17 ivg08 dma1 7 interrupt 18 ivg08 dma1 8 interrupt 19 ivg08 dma1 9 interrupt 20 ivg08 dma1 10 interrupt 21 ivg08 dma1 11 interrupt 22 ivg08 dma2 0 interrupt 23 ivg09 dma2 1 interrupt 24 ivg09 dma2 2 interrupt 25 ivg09 dma2 3 interrupt 26 ivg09 dma2 4 interrupt 27 ivg09 dma2 5 interrupt 28 ivg09 dma2 6 interrupt 29 ivg09 dma2 7 interrupt 30 ivg09 dma2 8 interrupt 31 ivg09 dma2 9 interrupt 32 ivg09 dma2 10 interrupt 33 ivg09 dma2 11 interrupt 34 ivg09 timer0 interrupt 35 ivg10 timer1 interrupt 36 ivg10 timer2 interrupt 37 ivg10 timer3 interrupt 38 ivg10 timer4 interrupt 39 ivg10 timer5 interrupt 40 ivg10 timer6 interrupt 41 ivg10 timer7 interrupt 42 ivg10 timer8 interrupt 43 ivg10 timer9 interrupt 44 ivg10 timer10 interrupt 45 ivg10 timer11 interrupt 46 ivg10 fio0 interrupt a 47 ivg11 fio0 interrupt b 48 ivg11 fio1 interrupt a 49 ivg11 fio1 interrupt b 50 ivg11 fio2 interrupt a 51 ivg11 fio2 interrupt b 52 ivg11 dma1 write/read 0 interrupt 53 ivg08 dma1 write/read1 interrupt 54 ivg08 dma2 write/read 0 interrupt 55 ivg09 dma2 write/read 1 interrupt 56 ivg09 imdma write/read 0 interrupt 57 ivg12 imdma write/read 1 interrupt 58 ivg12 watchdog timer 59 ivg13 reserved 60 ivg07 reserved 61 ivg07 supplemental 0 62 ivg07 supplemental 1 63 ivg07 1 peripheral interrupt channel number 2 default user ivg interrupt table 2. peripheral interrupt so urce reset state (continued) peripheral interrupt source chan 1 ivg 2
rev. prc | page 8 of 52 | april 2004 adsp-bf561 preliminary technical data the sic allows further control of event processing by providing six 32-bit interrupt cont rol and status regist ers. each register contains a bit corresponding to each of the peripheral interrupt events shown in table 2 . ? sic interrupt mask register (sic_imask0, sic_imask1) C this register controls th e masking and unmasking of each peripheral interrupt event. when a bit is set in the reg- ister, that peripheral even t is unmasked and will be processed by the system when asserted. a clea red bit in the register masks the peripheral event thereby preventing the processor from servicing the event. ? sic interrupt status regist er (sic_istat0, sic_istat1) C as multiple peripherals can be mapped to a single event, this register allows the softwa re to determine which periph- eral event source triggered the interrupt. a set bit indicates the peripheral is asserting the interrupt, a cleared bit indi- cates the peripheral is not asserting the event. ? sic interrupt wakeup enab le register (sic_iwr0, sic_iwr1)C by enabling the co rresponding bit in this reg- ister, each peripheral can be configured to wake up the processor, should the proce ssor be in a powered down mode when the event is generated. ( for more information, see dynamic power management on page 11. ) because multiple interrupt source s can map to a single general- purpose interrupt, multiple puls e assertions can occur simulta- neously, before or during interr upt processing for an interrupt event already detected on this interrupt input. the ipend reg- ister contents are monitored by the sic as the interrupt acknowledgement. the appropriate ilat register bit is set when an interrupt rising edge is detected (detection requ ires two core clock cycles). the bit is cleared when the respective ipend register bit is set. the ipend bit indicates that the event has entered into the proces- sor pipeline. at this point the cec will recognize and queue the next rising edge event on the corresponding event input. the minimum latency from the rising edge transition of the general- purpose interrupt to the ipend ou tput asserted is three core clock cycles; however, the latency can be much higher, depend- ing on the activity within and the mode of the processor. dma controllers the adsp-bf561 has multiple, independent dma controllers that support automated data transfers with minimal overhead for the dsp core. dma transfer s can occur between the adsp- bf561's internal memories and an y of its dma-capable periph- erals. additionally, dma tran sfers can be accomplished between any of the dma-capabl e peripherals and external devices connected to the external memory interfaces, including the sdram controller and the asynchronous memory control- ler. dma-capable peripherals include the sports, spi port, uart, and ppi. each individual dma-capable peripheral has at least one dedicated dma channel. the adsp-bf561 dma controllers support both 1-dimen- sional (1d) and 2-dimensional (2d) dma transfers. dma transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. the 2d dma capability support s arbitrary row and column sizes up to 64k elements by 64k elements, and arbitrary row and column step sizes up to +/ - 32k elements. furthermore, the column step size can be less th an the row step size, allowing implementation of interleaved da ta streams. this feature is especially useful in video appl ications where data can be de- interleaved on the fly. examples of dma types suppo rted by the adsp-bf561 dma controllers include: ? a single, linear buffer that stops upon completion ? a circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer ? 1-d or 2-d dma using a li nked list of descriptors ? 2-d dma using an array of descriptors, specifying only the base dma address wi thin a common page in addition to the dedicated peripheral dma channels, each dma controller has four memory dma channels provided for transfers between the various memories of the adsp-bf561 system. these enable tr ansfers of blocks of data between any of the memoriesincluding external sdram, rom, sram, and flash memorywith minimal processor intervention. memory dma transfers can be controlled by a very flexible descriptor- based methodology or by a stan dard register-based autobuffer mechanism. further, the adsp-bf561 has a fo ur channel internal memory dma (imdma) controller. the imdma controller allows data transfers between any of the internal l1 and l2 memories. watchdog timers each adsp-bf561 core includes a 32-bit timer, which can be used to implement a software watchdog function. a software watchdog can improve system avai lability by forc ing the proces- sor to a known state, via generation of a hardware reset, non- maskable interrupt (nmi), or general- purpose interrupt, if the timer expires before being rese t by software. the programmer initializes the count value of th e timer, enables the appropriate interrupt, then enables the timer. thereafter, the software must reload the counter before it counts to zero from the pro- grammed value. this protects th e system from remaining in an unknown state where software, wh ich would normally reset the timer, has stopped running due to an external noise condition or software error. after a reset, software can dete rmine if the watchdog was the source of the hardware reset by interrogating a status bit in the timer control register, which is set only upon a watchdog gener- ated reset. the timer is clocked by the syst em clock (sclk), at a maximum frequency of sclk.
adsp-bf561 preliminary technical data rev. prc | page 9 of 52 | april 2004 serial ports (sports) the adsp-bf561 incorporates two dual-channel synchronous serial ports (sport0 and sport1) for serial and multiproces- sor communications. the sports support the following features: ?i 2 s capable operation. ? bidirectional operation C each sport has two sets of inde- pendent transmit and receive pins, enabling eight channels of i 2 s stereo audio. ? buffered (8-deep) transmit an d receive ports C each port has a data register for transfe rring data words to and from other dsp components and shift registers for shifting data in and out of the data registers. ? clocking C each transmit and re ceive port can either use an external serial clock or generate its own, in frequencies ranging from (f sclk /131,070) hz to (f sclk /2) hz. ? word length C each sport supports serial data words from 3 to 32 bits in length, tr ansferred most-significant-bit first or least-significant-bit first. ? framing C each transmit and receive port can run with or without frame sync signals for each data word. frame sync signals can be generated internally or externally, active high or low, and with either of tw o pulsewidths and early or late frame sync. ? companding in hardware C each sport can perform a-law or -law companding according to itu recommen- dation g.711. companding can be selected on the transmit and/or receive channel of the sport without additional latencies. ? dma operations with single-cycle overhead C each sport can automatically receive and tr ansmit multiple buffers of memory data. the dsp can link or chain sequences of dma transfers between a sport and memory. ? interrupts C each transmit and receive port generates an interrupt upon completing the transfer of a data word or after transferring an entire data buffer or buffers through dma. ? multichannel capability C each sport supports 128 chan- nels out of a 1024-channel wind ow and is compatible with the h.100, h.110, mvip-90, and hmvip standards. serial peripheral interface (spi) ports the adsp-bf561 has one spi-comp atible ports that enable the processor to communicate with multiple spi-compatible devices. the spi interface uses three pins for transferring data: two data pins (master output-slave input, mosix, and master input- slave output, miso) and a clock pin (serial clock, sck). one spi chip select input pin (spiss ) let other spi devices select the dsp, and seven spi chip select output pins (spisel7C1) let the dsp select other spi devices. th e spi select pins are reconfig- ured programmable flag pins. using these pins, the spi ports provide a full duplex, synchronou s serial interface, which sup- ports both master and slave modes and multimaster environments. each spi ports baud rate and clock phase/polarities are pro- grammable (see spi clock rate equation), and each has an integrated dma controlle r, configurable to support transmit or receive data streams. the spis dma controller can only service unidirectional accesses at any given time. during transfers, the spi port s simultaneously transmit and receive by serially shifting data in and out on their two serial data lines. the serial clock line synchronizes the shifting and sampling of data on the two serial data lines. uart port the adsp-bf561 provides a full duplex universal asynchro- nous receiver/transmitter (uart) ports (uart0 and uart1) fully compatible with pc-standard uarts. the uart ports provide a simplified uart interface to other peripherals or hosts, supporting full duplex , dma supported, asynchronous transfers of serial data. each ua rt port includes support for 5 to 8 data bits; 1 or 2 stop bits; an d none, even, or odd parity. the uart ports support two modes of operation, as follows: ? pio (programmed i/o) C the processor sends or receives data by writing or readin g i/o-mapped uatx or uarx registers, respectively. the data is double-buffered on both transmit and receive. ? dma (direct memory acce ss) C the dma controller transfers both transmit and re ceive data. this reduces the number and frequency of interrupts required to transfer data to and from memory. ea ch uart has two dedicated dma channels, one for transmit and one for receive. these dma channels have lower prio rity than most dma chan- nels because of their relatively low service rates. each uart ports baud rate (see uart clock rate equation), serial data format, error code generation and status, and inter- rupts are programmable. in the uart clock rate equation, the divisor (d) can be 1 to 65536. the uart programmable features include: ? supporting bit rates ranging from (f sclk / 1048576) to (f sclk /16) bits per second. ? supporting data formats from 7 to12 bits per frame. ? both transmit and receive operations can be configured to generate maskable interrupts to the processor. in conjunction with the general- purpose timer functions, auto- baud detection is supported. spi clock rate f sclk 2 spibaud ----------------------------------- = uart clock rate f sclk 16 d ---------------- =
rev. prc | page 10 of 52 | april 2004 adsp-bf561 preliminary technical data the capabilities of uart0 are further extended with support for the infrared data associatio n (irda?) serial infrared phys- ical layer link specification (sir) protocol. programmable flags (pfx) the adsp-bf561 has 48 bi-directional, general-purpose i/o, programmable flag (pf47C0) pins. the programmable flag pins have special functions for spi port operation. each pro- grammable flag can be individu ally controlled as follows by manipulation of the flag control, status, and interrupt registers: ? flag direction control register C specifies the direction of each individual pfx pin as input or output. ? flag control and status regist ers C rather than forcing the software to use a read-modify- write process to control the setting of individual flags, the adsp-bf561 employs a "write one to set" and "write one to clear" mechanism that allows any combination of individual flags to be set or cleared in a single instruction, without affecting the level of any other flags. two control registers are provided, one register is written to in order to set flag values while another register is written to in order to clear flag values. reading the flag status register allows software to interro- gate the sense of the flags. ? flag interrupt mask register s C the flag interrupt mask registers allow each individual pfx pin to function as an interrupt to the processor. si milar to the flag control reg- isters that are used to set and clear individual flag values, one flag interrupt mask register sets bits to enable inter- rupt function, and the other flag interrupt mask register clears bits to disable interrupt function. pfx pins defined as inputs can be configured to generate hardware interrupts, while output pfx pins can be configured to generate soft- ware interrupts. ? flag interrupt sensitivity re gisters C the flag interrupt sensitivity registers specify whether individual pfx pins are level- or edge-sensitive and specify-if edge-sensitive- whether just the rising edge or both the rising and falling edges of the signal are signific ant. one register selects the type of sensitivity, and one re gister selects which edges are significant for edge-sensitivity. timers there are fourteen (14) programm able timer units in the adsp- bf561. twelve general-purpose time rs have an external pin that can be configured either as a pulse width modulator (pwm) or timer output, as an input to lock the timer, or for measuring pulse widths of external events. each of the twelve general-pur- pose timer units can be indepe ndently programm ed as a pwm, internally or externally clocked timer, or pulse width counter. the general-purpose timer units can be used in conjunction with the uart to measure the width of the pulses in the data stream to provide an auto-baud detect function for a serial channel. the general-purpose timers can generate interrupts to the pro- cessor core providing periodic events for synchronization, either to the processor clock or to a count of external signals. in addition to the twelve genera l-purpose programmable timers, another timer is also provided fo r each core. these extra timers are clocked by the internal processor clock (cclk) and is typi- cally used as a system tick cl ock for generation of operating system periodic interrupts. parallel peripheral interface the processor provides two parallel peripheral interfaces (ppi) that can connect directly to parallel a/d and d/a converters, itu-r-601/656 video encoders and decoders, and other general purpose peripherals. each ppi consists of a dedicated input clock pin, up to 3 frame synchronization pins, and up to 16 data pins. in itu-r 656 mode, the ppi receives and parses a data stream of 8- bit or 10-bit data elements . on-chip decode of embedded preamble control and synchronization information is supported. general purpose mode descriptions the general-purpose modes of the ppi are intended to suit a wide variety of data capture and transmission applications. the modes are divided into four main categories, each allowing up to 16 bits of data tran sfer per ppi_clk cycle: ? data receive with interna lly generated frame syncs. ? data receive with externally generated frame syncs. ? data transmit with internally generated frame syncs. ? data transmit with externally generated frame syncs. input mode these modes support adc/dac connections, as well as video communication with hardware signaling. many of the modes support more than one level of frame synchronization. if desired, a programmable delay can be inserted between asser- tion of a frame sync and reception / transmission of data. itu -r 656 mode descriptions three distinct itu-r 656 modes are supported: ?active video only mode ? vertical blanking only mode ? entire field mode active video only mode in this mode, the ppi does not read in any data between the end of active video (eav) and star t of active video (sav) pream- ble symbols, or any data present during the vertical blanking intervals. in this mode, the cont rol byte sequences are not stored to memory; they are filtered by the ppi. vertical blanking interval mode in this mode, the ppi only transfers vertical blanking interval (vbi) data, as well as horizontal blanking information and con- trol byte sequences on vbi lines.
adsp-bf561 preliminary technical data rev. prc | page 11 of 52 | april 2004 entire field mode in this mode, the entire incoming bitstream is read in through the ppi. this includes active video, control preamble sequences, and ancillary data that may be embedded in horizontal and ver- tical blanking intervals. though not explicitly supported , itu,-656 output functionality can be achieved by setting up the entire frame structure (includ- ing active video, blanking and control information) in memory and streaming the data out of the ppi in a frame sync-less mode. the processors 2d dma features facilitate this transfer by allowing the static frame buffer (blanking and control codes) to be placed in memory once, and simply updating the active video information on per-frame basis. these modes support adc/dac connections, as well as video communication with hardware signaling. many of the modes support more than one level of frame synchronization. if desired, a programmable delay can be inserted between asser- tion of a frame sync and reception/transmission of data. dynamic power management the adsp-bf561 provides four operating modes, each with a different performance/power pr ofile. in addition, dynamic power management provides the control functions to dynami- cally alter the processor core supply voltage, further reducing power dissipation. control of clocking to each of the adsp- bf561 peripherals also reduce s power consumption. see table 3 for a summary of the power settings for each mode. full-on operating mode C maximum performance in the full-on mode, the pll is enabled and is not bypassed, providing capability for maximum operational frequency. this is the default execution state in which maximum performance can be achieved. the processor cores and all enabled peripherals run at full speed. active operating mode C moderate power savings in the active mode, the pll is enabled but bypassed. because the pll is bypassed, the processo rs core clock (cclk) and sys- tem clock (sclk) run at the input clock (clkin) frequency. in this mode, the clkin to cclk multiplier ratio can be changed, although the changes are not realized until the full-on mode is entered. dma access is available to appropriately configured l1 memories. in the active mode, it is possible to disable the pll through the pll control register (pll_ctl). if disabled, the pll must be re-enabled before transitioning to the full-on or sleep modes. hibernate operating modemaximum static power savings the hibernate mode maximizes static power savings by dis- abling the voltage and clocks to the processor core (cclk) and to all the synchronous peripheral s (sclk). the internal voltage regulator for the processor can be shut off by writing b#00 to the freq bits of the vr_ctl regi ster. this disables both cclk and sclk. furthermore, it sets the internal power supply volt- age (v ddint ) to 0 v to provide the lowest static power dissipation. any critical information stored internally (memory contents, register contents, etc.) must be written to a non-vola- tile storage device prior to remo ving power if the processor state is to be preserved. since v ddext is still supplied in this mode, all of the external pins tri-state, unless otherwise specified. this allows other devices that may be connected to the processor to have power still applied without drawing unwanted current. the internal supply regulator can be woken up by asserting the reset pin. sleep operating modehigh dynamic power savings the sleep mode reduces power dissipation by disabling the clock to the processor core ( cclk). the pll and system clock (sclk), however, continue to operate in this mode. typically an external event will wake up the processor. when in the sleep mode, assertion of wakeup will ca use the processor to sense the value of the bypass bit in the pll control register (pll_ctl). when in the sleep mode, system dma access to l1 memory is not supported. deep sleep operating modemaximum dynamic power savings the deep sleep mode maximizes power savings by disabling the clocks to the processor cores (cclk) and to all synchronous peripherals (sclk). asynchronous peripherals will not be able to access internal resources or external memory. this powered- down mode can only be exited by assertion of the reset interrupt (reset ). if bypass is disabled, the processor will transition to the full on mode. if bypass is en abled, the processor will tran- sition to the active mode. power savings as shown in table 4 , the adsp-bf561 supports two different power domains. the use of multiple power domains maximizes flexibility, while maintaining compliance with industry stan- dards and conventions. by isolating the internal logic of the adsp-bf561 into its own power domain, separate from the i/o, table 3. power settings mode pll pll bypassed core clock (cclk) system clock (sclk) core power full on enabled no enabled enabled on active enabled/ disabled yes enabled enabled on sleep enabled C disabled enabled on deep sleep disabled C disabled disabled on hibernate disabled C disabled disabled off table 3. power settings (continued) mode pll pll bypassed core clock (cclk) system clock (sclk) core power
rev. prc | page 12 of 52 | april 2004 adsp-bf561 preliminary technical data the processor can take advantage of dynamic power manage- ment, without affecting the i/o devices. there are no sequencing requirements for the various power domains. the power dissipated by a processo r is largely a function of the clock frequency of the processor and the square of the operating voltage. for example, reducing the clock frequency by 25% results in a 25% reduction in dynamic power dissipation, while reducing the voltage by 25% reduces dynamic power dissipation by more than 40%. further, thes e power savings are additive, in that if the clock frequency and supply voltage are both reduced, the power savings can be dramatic. the dynamic power management feature of the adsp-bf561 allows both the processors input voltage (v ddint ) and clock frequency (f cclk ) to be dynamically controlled. the savings in power dissipation can be modeled using the power savings factor and % power savings calculations. the power savings factor is calculated as: where the variables in the equations are: ?f cclknom is the nominal core clock frequency ?f cclkred is the reduced core clock frequency ?v ddintnom is the nominal internal supply voltage ?v ddintred is the reduced internal supply voltage ?t nom is the duration running at f cclknom ?t red is the duration running at f cclkred the percent power savings is calculated as: voltage regulation the adsp-bf561 processor provides an on-chip voltage regula- tor that can generate processor core voltage levels 0.85v(-5% / +10%) to 1.2v(-5% / +10%) from an external 2.25 v to 3.6 v supply. figure 4 shows the typical external components required to complete the powe r management system. the regu- lator controls the internal logic voltage levels and is programmable with the voltag e regulator control register (vr_ctl) in increments of 50 mv. to reduce standby power consumption, the internal voltag e regulator can be programmed to remove power to the processo r core while keeping i/o power (v ddext ) supplied. while in hibernation, v ddext can still be applied, eliminating the need for external buffers. the voltage regulator can be activated from this powerdown state by assert- ing reset , which will then initiate a boot sequence. the regulator can also be disabled and bypassed at the users discretion. table 4. adsp-bf561 power domains power domain vdd range all internal logic v ddint i/o v ddext figure 4. voltage regulator circuit power savings factor f cclkred f cclknom --------------------- v ddintred v ddintnom -------------------------- ?? ?? 2 t red t nom ------------ - ? ? ? ? = % power savings 1 power savings factor ? () 100% =
adsp-bf561 preliminary technical data rev. prc | page 13 of 52 | april 2004 clock signals the adsp-bf561 can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. if an external clock is used, it should be a ttl compatible signal and must not be halted, changed, or operated below the speci- fied frequency during normal operation. this signal is connected to the processors cl kin pin. when an external clock is used, the xtal pin must be left unconnected. alternatively, because the adsp -bf561 includes an on-chip oscillator circuit, an external crystal may be used. the crystal should be connected across the clkin and xtal pins, with two capacitors connected as shown in figure 5 capacitor values are dependent on crystal type and should be specified by the crystal manufa cturer. a parallel-resonant, fun- damental frequency, microprocessor-grade crystal should be used. as shown in figure 6 , the core clock ( cclk) and system peripheral clock (sclk) are derived from the input clock (clkin) signal. an on-chip pll is capable of multiplying the clkin signal by a user programm able 1x to 63x multiplication factor. the default multiplier is 10x, but it can be modified by a software instruction sequence. on-the-fly frequency changes can be effected by simply wr iting to the pll_div register. all on-chip peripherals are clocked by the system clock (sclk). the system clock frequency is programmable by means of the ssel3C0 bits of the pll_div re gister. the values programmed into the ssel fields define a divide ratio between the pll output (vco) and the system clock. sclk divider values are 1 through 15. table 5 illustrates typical system clock ratios: the maximum frequency of the system clock is f sclk . note that the divisor ratio must be chosen to limit the system clock fre- quency to its maximum of f sclk . the ssel value can be changed dynamically without any pll lo ck latencies by writing the appropriate values to the pll divisor register (pll_div). the core clock (cclk) freque ncy can also be dynamically changed by means of the csel[1C0] bits of the pll_div regis- ter. supported cclk divider ratios are 1, 2, 4, and 8, as shown in table 6 . this programmable core cloc k capability is useful for fast core frequency modifications. booting modes the adsp-bf561 has three mechanisms (listed in table 7 ) for automatically loading internal l1 instruction memory after a reset. a fourth mode is provided to execute from external mem- ory, bypassing the boot sequence. figure 5. external crystal connections figure 6. frequency mo dification methods clkin clkout xtal pll 1 -63 1:15 1, 2, 4, 8 vco sclk cclk sclk 13 3 m hz clkin ?fine? adjustment re qui re s pll seq uencing ?coarse? adjustment on-the -fly cc l k sclk table 5. example system clock ratios signal name ssel[3C0] divider ratio vco/sclk example frequency ratios (mhz) vco sclk 0001 1:1 100 100 0110 6:1 300 50 1010 10:1 500 50 table 6. core clock ratios signal name csel[1C0] divider ratio vco/cclk example frequency ratios vco cclk 00 1:1 500 500 01 2:1 500 250 10 4:1 200 50 11 8:1 200 25 table 7. booting modes bmode1C0 description 00 execute from 16-bit external memory (bypass boot rom) 01 boot from 8/16-bit flash 10 reserved 11 boot from spi serial rom (16-bit address range)
rev. prc | page 14 of 52 | april 2004 adsp-bf561 preliminary technical data the bmode pins of the reset configuration register, sampled during power-on resets and so ftware-initiated resets, imple- ment the following modes: ? execute from 16-bit external memory - execution starts from address 0x2000 0000 with 16-bit packing. the boot rom is bypassed in this mode. all configuration settings are set for the slowest device possible (3-cycle hold time, 15-cycle r/w access time s, 4-cycle setup). ? boot from 8/16-bit external flash memory C the 8/16-bit flash boot routine located in boot rom memory space is set up using asynchronous me mory bank 0. all configura- tion settings are set for the slowest device possible (3-cycle hold time; 15-cycle r/w acce ss times; 4-cycle setup). ? boot from spi serial eeprom (16-bit addressable) C the spi uses the pf2 output pin to select a single spi eprom device, submits a read comm and at address 0x0000, and begins clocking data into th e beginning of l1 instruction memory. a 16-bit addressable spi-compatible eprom must be used. for each of the boot modes, a boot loading protocol is used to transfer program and data blocks, from an external memory device, to their specified memory locations. multiple memory blocks may be loaded by any boot sequence. once all blocks are loaded, core a program executio n commences from the start of l1 instruction sram (0xffa0 0 000). core b remains in a held- off state until a certain register bit is cleared. after that, core b will start execution at address 0xff60 0000. in addition, bit 4 of the reset configuration register can be set by application code to bypass the normal boot sequence during a software reset. for this case, the processor jumps directly to the beginning of l1 instruction memory. instruction set description the blackfin processor family a ssembly language instruction set employs an algebraic syntax that was designed for ease of coding and readability. the instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to a very small final memory si ze. the instruction set also pro- vides fully featured multifunctio n instructions that allow the programmer to use many of the processor core resources in a single instruction. coupled with many features more often seen on microcontrollers, this instruction set is very efficient when compiling c and c++ source code. in addition, the architecture supports both a user (algorithm /application code) and a super- visor (o/s kernel, device drivers, debuggers, isrs) mode of operations, allowing multiple levels of access to core processor resources. the assembly language, which takes advantage of the proces- sors unique architecture, offers the following advantages: ? seamlessly integrated dsp/cpu features are optimized for both 8-bit and 16-bit operations. ? a multi-issue load/store modified-harvard architecture, which supports two 16-bit mac or four 8-bit alu + two load/store + two pointer updates per cycle. ? all registers, i/o, and memory are mapped into a unified 4g-byte memory space provid ing a simplified program- ming model. ? microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and extraction; integer operations on 8-, 16-, and 32-bit data-types; and separate user and ker- nel stack pointers. ? code density enhancements, which include intermixing of 16- and 32-bit instructions (n o mode switching, no code segregation). frequently used instructions are encoded as 16-bits. development tools the adsp-bf561 is supported with a complete set of crosscore tm software and hardware development tools, including analog devices emulators and the visualdsp++? development environment. the sa me emulator hardware that supports other analog devices pr ocessors also fully emulates the adsp-bf561. the visualdsp++ project manage ment environment lets pro- grammers develop and debug an application. this environment includes an easy-to-use assembler that is based on an algebraic syntax, an archiver (librarian/library builder), a linker, a loader, a cycle-accurate instruction-leve l simulator, a c/c++ compiler, and a c/c++ run-time library that includes dsp and mathemat- ical functions. a key point fo r these tools is c/c++ code efficiency. the compiler has been developed for efficient trans- lation of c/c++ code to blac kfin assembly. the blackfin processor has architectural featur es that improve the efficiency of compiled c/c++ code. the visualdsp++ debugger has a number of important fea- tures. data visualization is enha nced by a plotting package that offers a significant level of flexibility. this graphical representa- tion of user data enables the programmer to quickly determine the performance of an algorithm. as algorithms grow in com- plexity, this capability can have increasing significance on the designers development schedule, increasing productivity. sta- tistical profiling enables the pr ogrammer to non intrusively poll the processor as it is running the program. this feature, unique to visualdsp++, enables the so ftware developer to passively gather important code execution metrics without interrupting the real-time characteristics of the program. essentially, the developer can identify bottlenecks in software quickly and effi- ciently. by using the profiler , the programmer can focus on those areas in the program that impact performance and take corrective action. debugging both c/c++ and assembly programs with the visu- aldsp++ debugger, programmers can: ? view mixed c/c++ and assembly code (interleaved source and object information) ? insert breakpoints ? set conditional breakpoints on registers, memory, and stacks ? trace instruction execution ? perform linear or statistical profiling of program execution
adsp-bf561 preliminary technical data rev. prc | page 15 of 52 | april 2004 ? fill, dump, and graphically plot the contents of memory ? perform source level debugging ? create custom debugger windows the visualdsp++ ide lets programmers define and manage software development. its dialog boxes and prop erty pages let programmers configure and mana ge all development tools, including color syntax highlighting in the visualdsp++ edi- tor. these capabilities permit programmers to: ? control how the development tools process inputs and generate outputs. ? maintain a one-to-one correspondence with the tools command line switches. the visualdsp++ kernel (vdk) incorporates scheduling and resource management tailored sp ecifically to address the mem- ory and timing constraints of embedded, real-time programming. these ca pabilities enable engineers to develop code more effectively, eliminat ing the need to start from the very beginning, when developing new application code. the vdk features include threads, critical and unscheduled regions, semaphores, events, and device flags. the vdk also supports priority-based, pre-em ptive, cooperative and time- sliced scheduling approaches. in addition, the vdk was designed to be scalable. if the application does not use a specific feature, the support code for that feature is excluded from the target system. because the vdk is a library, a developer can decide whether to use it or not. the vdk is integrated into the visualdsp++ development environmen t, but can also be used with standard command-line tools. when the vdk is used, the development environment assists the develope r with many error-prone tasks and assists in managing system resources, automating the gen- eration of various vdk based objects, and visualizing the system state, when debugging an application that uses the vdk. vcse is analog devices techno logy for creati ng, using, and reusing software components (independent modules of sub- stantial functionality) to quickly and reliably assemble software applications. download compon ents from the web and drop them into the application. pu blish component archives from within visualdsp++. vcse su pports component implementa- tion in c/c++ or assembly language. use the expert linker to visua lly manipulate the placement of code and data on the embedded system. view memory utiliza- tion in a color-coded graphical fo rm, easily move code and data to different areas of the processor or external memory with the drag of the mouse, examine run time stack and heap usage. the expert linker is fully compatible with existing linker definition file (ldf), allowing the develo per to move between the graphi- cal and textual environments. analog devices emulators use the ieee 1149.1 jtag test access port of the adsp-bf561 to mo nitor and control the target board processor during emulatio n. the emulator provides full- speed emulation, allowing inspec tion and modification of mem- ory, registers, and processor st acks. non intrusive in-circuit emulation is assured by the use of the processors jtag inter- facethe emulator does not affe ct target system loading or timing. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the bl ackfin processor family. third party software tools include dsp libraries, real-time operating systems, and block diagram design tools. designing an emulator-compatible processor board (target) the analog devices family of em ulators are tools that every sys- tem developer needs to test and debug hardware and software systems. analog devices has supplied an ieee 1149.1 jtag test access port (tap) on the adsp-bf561. the emulator uses the tap to access the internal fe atures of the processor, allow- ing the developer to load co de, set breakpoints, observe variables, observe memory, and examine registers. the proces- sor must be halted to send da ta and commands, but once an operation has been completed by the emulator, the processor is set running at full speed with no impact on system timing. to use these emulators, the target board must include a header that connects the processors jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor conne ctions, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see the ee-68: analog devices jt ag emulation technical reference on the analog devices web site ( www.analog.com ) use site search on ee-68. this document is updated regularly to keep pace with improvements to emulator support. to use these emulators, the target board must include a header that includes a header that conn ects the processors jtag port to the emulation. additional information this data sheet provides a gene ral overview of the adsp-bf561 architecture and functionality. for detailed information on the blackfin dsp family core architec ture and instruction set, refer to the adsp-bf561 hardware referenc e and the blackfin family instruction set reference.
rev. prc | page 16 of 52 | april 2004 adsp-bf561 preliminary technical data pin descriptions adsp-bf561 pin definiti ons are listed in table 8 . unused inputs should be tied or pulled to v ddext or gnd. table 8. pin descriptions block pin name type signals function driver type pull-up/down requirement ebiu addr[25:2] o 24 address bus for async/sync access a none data[31:0] i/o 32 data bus for async/sync access a none abe [3:0]/sdqm[3:0] o 4 byte enables/data masks for async /sync access anone bg o 1 bus grant a none br i1 bus request - pull-up required if function not used bgh o 1 bus grant hang a none ebiu (sdram) sras o 1 row address strobe a none scas o 1 column address strobe a none swe o1 write enable a none scke o 1 clock enable a none sclk0/clkout o 1 clock output pin 0 b none sclk1 o 1 clock output pin 1 b none sa10 o 1 sdram a10 pin a none sms[3:0] o 4 bank select a none ebiu (async) ams[3:0] o 4 bank select a none ardy i 1 hardware ready control - pull-up required if function not used aoe o 1 output enable a none awe o1 write enable a none are o 1 read enable a none ppi1 ppi1d[15:8] /pf[47:40] i/o 8 ppi data / programmable flag pins c software configurable, none ppi1d[7:0] i/o 8 ppi data pins c software configurable, none ppi1clk i 1 ppi clock - software configurable, none ppi1sync1/ tmr8 i/o 1 ppi sync / timer c software configurable, none ppi1sync2/ tmr9 i/o 1 ppi sync / timer c software configurable, none ppi1sync3 i/o 1 ppi sync c software configurable, none ppi2 ppi2d[15:8] /pf[39:32] i/o 8 ppi data / programmable flag pins c software configurable, none ppi2d[7:0] i/o 8 ppi data pins c software configurable, none ppi2clk i 1 ppi clock - software configurable, none ppi2sync1/ tmr10 i/o 1 ppi sync / timer c software configurable, none ppi2sync2/ tmr11 i/o 1 ppi sync / timer c software configurable, none ppi2sync3 i/o 1 ppi sync c software configurable, none jtag emu o 1 emulation output c none tck i 1 jtag clock - internal pull-down tdo o 1 jtag serial data out c none tdi i 1 jtag serial data in - internal pull-down tms i 1 jtag mode select - internal pull-down trst i 1 jtag reset - external down necessary if jtag not used
adsp-bf561 preliminary technical data rev. prc | page 17 of 52 | april 2004 uart rx/pf27 i/o 1 uart receive / programmable flag c software configurable, no pull-up/down necessary tx/pf26 i/o 1 uart transmit / programmable flag c software configurable, no pull-up/down necessary spi mosi i/o 1 master out slave in c software configurable, no pull-up/down necessary miso i/o 1 master in slave out c pull-up is necessary if booting via spi sck i/o 1 spi clock d software configurable, no pull-up/down necessary sport0 rsclk0/pf28 i/o 1 spor t0 / programmable flag d software configurable, no pull-up/down necessary rfs0/pf19 i/o 1 sport0 receive frame sync / programmable flag c software configurable, no pull-up/down necessary dr0pri i 1 sport0 receive data primary - software configurable, no pull-up/down necessary dr0sec/pf20 i/o 1 sport0 receive data secondary / programmable flag c software configurable, no pull-up/down necessary tsclk0/pf29 i/o 1 sport0 transmit serial clock / programmable flag d software configurable, no pull-up/down necessary tfs0/pf16 i/o 1 sport0 transmit frame sync / programmable flag c software configurable, no pull-up/down necessary dt0pri/pf18 i/o 1 sport0 transmit data primary / programmable flag c software configurable, no pull-up/down necessary dt0sec/pf17 i/o 1 sport0 transmit data secondary / programmable flag c software configurable, no pull-up/down necessary sport1 rsclk1/pf30 i/o 1 spor t1 / programmable flag d software configurable, no pull-up/down necessary rfs1/pf24 i/o 1 sport1 receive frame sync / programmable flag c software configurable, no pull-up/down necessary dr1pri i 1 sport1 receive data primary - software configurable, no pull-up/down necessary dr1sec/pf25 i/o 1 sport1 receive data secondary / programmable flag c software configurable, no pull-up/down necessary tsclk1/pf31 i/o 1 sport1 transmit serial clock / programmable flag d software configurable, no pull-up/down necessary tfs1/pf21 i/o 1 sport1 transmit frame sync / programmable flag c software configurable, no pull-up/down necessary dt1pri/pf23 i/o 1 sport1 transmit data primary / programmable flag c software configurable, no pull-up/down necessary dt1sec/pf22 i/o 1 sport1 transmit data secondary / programmable flag c software configurable, no pull-up/down necessary table 8. pin descriptions (continued) block pin name type signals function driver type pull-up/down requirement
rev. prc | page 18 of 52 | april 2004 adsp-bf561 preliminary technical data pf/timer pf15/ext clk i/o 1 programmable flag / external timer clock input c software configurable, no pull-up/down necessary pf14 i/o 1 programmable flag c software configurable, no pull-up/down necessary pf13 i/o 1 programmable flag c software configurable, no pull-up/down necessary pf12 i/o 1 programmable flag c software configurable, no pull-up/down necessary pf11 i/o 1 programmable flag c software configurable, no pull-up/down necessary pf10 i/o 1 programmable flag c software configurable, no pull-up/down necessary pf9 i/o 1 programmable flag c software configurable, no pull-up/down necessary pf8 i/o 1 programmable flag c software configurable, no pull-up/down necessary pf7/spisel7/ tmr7 i/o 1 programmable flag / spi select / timer c software configurable, no pull-up/down necessary pf6/spisel6/ tmr6 i/o 1 programmable flag / spi select / timer c software configurable, no pull-up/down necessary pf5/spisel5/ tmr5 i/o 1 programmable flag / spi select / timer c software configurable, no pull-up/down necessary pf4/spisel4/ tmr4 i/o 1 programmable flag / spi select / timer c software configurable, no pull-up/down necessary pf3/spisel3/ tmr3 i/o 1 programmable flag / spi select / timer c software configurable, no pull-up/down necessary pf2/spisel2/ tmr2 i/o 1 programmable flag / spi select / timer c software configurable, no pull-up/down necessary pf1/spisel1/ tmr1 i/o 1 programmable flag / spi select / timer c software configurable, no pull-up/down necessary pf0/spiss/ tmr0 i/o 1 programmable flag / slave spi select / timer c software configurable, no pull-up/down necessary clock generator clkin i 1 clock input - needs to be at a level or clocking xtal o 1 crystal connection - none mode controls reset i 1 chip reset signal - always active if core power on sleep o 1 sleep c none bmode[1:0] i 2 dedicated mode pin, configures the boot mode that is employed following a hardware reset or software reset - pull-up or pu ll-down required bypass i 1 pll bypass control - pu ll-up or pull-down required nmi0 i 1 non maskable interrupt core a - pull-down required if function not used nmi1 i 1 non maskable interrupt core b - pull-down required if function not used regulator vrout1-0 o 2 regulation output - n/a table 8. pin descriptions (continued) block pin name type signals function driver type pull-up/down requirement
adsp-bf561 preliminary technical data rev. prc | page 19 of 52 | april 2004 supplies vddext p 23 power supply - n/a vddint p 14 power supply - n/a gnd g 41 power supply return - n/a no connection nc 2 nc - n/a total pins 256 table 8. pin descriptions (continued) block pin name type signals function driver type pull-up/down requirement
rev. prc | page 20 of 52 | april 2004 adsp-bf561 preliminary technical data specifications note that component specificatio ns are subject to change with- out notice. recommended operating conditions electrical characteristics parameter parameter minimum nominal maximum unit v ddint internal supply voltage 0.8 1.2 tbd v v ddext external supply voltage 2.25 2.5 or 3.3 3.6 v v ih high level input voltage 1 , @ v ddext =maximum 1 the adsp-bf561 is 3.3 v tolerant (alwa ys accepts up to 3.6 v maximum v ih ), but voltage compliance (on outputs, v oh ) depends on the input v ddext , because v oh (maximum) approximately equals v ddext (maximum). this 3.3 v to lerance applies to bi-directi onal and input only pins. 2.0 3.6 v v il low level input voltage 2 , @ v ddext =minimum C0.3 0.6 v t ambient ambient operating temperature industrial -40 85 oc commercial 0 70 oc parameter test conditions minimum maximum unit v oh high level output voltage 1 @ v ddext =3.0v, i oh = C0.5 ma 2.4 v v ol low level output voltage 1 @ v ddext =3.0v, i ol = 2.0 ma 0.4 v i il low level input current 2 @ v ddext =maximum, v in = 0 v -10 v i ih high level input current 3 @ v ddext =maximum, v in = v dd maximum 10 a i ih high level input current 4 @ v ddext =maximum, v in = v dd maximum 50 a i ozh three-state leakage current 5 @ v ddext = maximum, v in = v dd maximum 10 a i ozl three-state leakage current 5 @ v ddext = maximum, v in = 0 v -10 a c in input capacitance 6, 7 f in = 1 mhz, t ambient = 25c, v in = 2.5 v tbd pf 1 applies to output an d bidirectional pins. 2 applies to all input pins. 3 applies to all input pins exce pt tck, tdi, tms, and trst . 4 applies to tck, tdi, tms, and trst . 5 applies to three-statable pins. 6 applies to all signal pins. 7 guaranteed, but not tested.
adsp-bf561 preliminary technical data rev. prc | page 21 of 52 | april 2004 absolute maximum ratings esd sensitivity internal (core) supply voltage 1 (v ddint ) 1 stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions greater than those indicated in th e operational sections of this specification is not implied. exposure to absolute maxi mum rating conditions for extended periods may affect device reliability. C0.3 v to +1.4 v external (i/o) supply voltage 1 (v ddext )C0.3 v to +3.8 v input voltage 1 C0.5 v to 3.6 v output voltage swing 1 C0.5 v to v ddext +0.5 v load capacitance 1 ,2 2 for proper sdram controller operation, th e maximum load capacitance is 50 pf (at 3.3v) or 30 pf (at 2.5v) fo r addr25-2, data31-0, abe3-0 /sdqm3-0, clkout, scke, sa10, sras , scas , swe , and sms . 200 pf core clock (cclk) 1 adsp-bf561skbcz600 600 mhz adsp-bf561skbcz500 500 mhz system clock (sclk) 1 133 mhz storage temperature range 1 C65oc to +150oc junction temperature under bias 125oc lead temperature (5 seconds) 1 185oc caution esd (electrostatic discharge) se nsitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equi pment and can discharge without detection. although the adsp-bf561 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precau- tions are recommended to avoid performanc e degradation or loss of functionality.
rev. prc | page 22 of 52 | april 2004 adsp-bf561 preliminary technical data timing specifications table 9 and table 12 describe the timing requirements for the adsp-bf561 clocks. take care in selecting msel, ssel, and csel ratios so as not to exceed the maximum core clock, system clock and voltage controlled os cillator (vco) operating fre- quencies, as described in absolute maximum ratings on page 21 . table 12 describes phase-lock ed loop operating conditions. table 9. core and system cloc k requirementsadsp-bf561skbcz500 parameter minimum maximum unit t cclk core cycle period (v ddint =1.4 vC 50 mv) na ns t cclk core cycle period (v ddint =1.35 vC5%) na ns t cclk core cycle period (v ddint =1.2 vC5%) 2 ns t cclk core cycle period (v ddint =1.1 vC5%) 2.25 ns t cclk core cycle period (v ddint =1.0 vC5%) 2.70 ns t cclk core cycle period (v ddint =0.9 vC5%) 3.20 ns t cclk core cycle period (v ddint =0.8 v) 4.00 ns table 10. core and system cloc k requirementsadsp-bf561skbcz600x parameter minimum maximum unit t cclk core cycle period (v ddint =1.4 vC 50 mv) na ns t cclk core cycle period (v ddint =1.35 vC5%) na ns t cclk core cycle period (v ddint =1.2 vC5%) 1.66 ns t cclk core cycle period (v ddint =1.1 vC5%) 2.25 ns t cclk core cycle period (v ddint =1.0 vC5%) 2.70 ns t cclk core cycle period (v ddint =0.9 vC5%) 3.20 ns t cclk core cycle period (v ddint =0.8 v) 4.00 ns table 11. core and system cloc k requirementsadsp-bf561sbb600 parameter minimum maximum unit t cclk core cycle period (v ddint =1.4 vC 50 mv) na ns t cclk core cycle period (v ddint =1.35 vC5%) 1.66 ns t cclk core cycle period (v ddint =1.2 vC5%) 2.0 ns t cclk core cycle period (v ddint =1.1 vC5%) 2.25 ns t cclk core cycle period (v ddint =1.0 vC5%) 2.70 ns t cclk core cycle period (v ddint =0.9 vC5%) 3.20 ns t cclk core cycle period (v ddint =0.8 v) 4.00 ns table 12. phase-locked loop operating conditions parameter minimum maximum unit voltage controlled oscillator (vco) frequency 50 maximum cclk mhz
adsp-bf561 preliminary technical data rev. prc | page 23 of 52 | april 2004 clock and reset timing table 13 and figure 7 describe clock and reset operations. per figure 7 , combinations of clkin and clock multipliers must not select core/peripheral cl ocks in excess of 600/133 mhz. table 13. clock and reset timing parameter min max unit timing requirement s t ckin clkin period 25.0 100.0 ns t ckinl clkin low pulse 1 10.0 ns t ckinh clkin high pulse 1 10.0 ns t wrst reset asserted pulsewidth low 2 11 t ckin ns switching characteristics t sclk clkout period 3 7.5 4 ns 1 applies to bypass mode and non-bypass mode. 2 applies after power-up sequence is complete . at power-up, the processor s internal phase-locked loop requires no more than 2000 clkin cycles, while reset is asserted, assuming stable power supplies and clkin (not incl uding start-up time of external clock oscillator). 3 the figure below shows a x2 ratio between t ckin and t sclk , but the ratio has many programmable options. for more information, see the system design chapter of the adsp- bf561 hardware reference . 4 t sclk must always also be larger than t c c lk . figure 7. clock and reset timing t sclkd clkout reset clkin t ckinh t ckin t ckinl t sclk t wrst
rev. prc | page 24 of 52 | april 2004 adsp-bf561 preliminary technical data asynchronous memory read cycle timing table 14. asynchronous memory read cycle timing parameter min max unit timing requirements t sdat data15C0 setup before clkout 2.1 ns t hdat data15C0 hold after clkout 0.8 ns t sardy ardy setup before clkout 4.0 ns t hardy ardy hold after clkout 0.0 ns switching characteristic t do output delay after clkout 1 6.0 ns t ho output hold after clkout 1 0.8 ns 1 output pins include ams 3C0, abe 3C0, addr25C2, aoe , are . figure 8. asynchronous memory read cycle timing t do t sdat clkout amsx abe1C0 t ho be, address read t hdat data15?0 aoe t do t sardy t hardy access extended 3cycles hold 1cycle are t hardy ardy addr19?1 setup 2cycles programmed read access 4cycles t ho t sardy
adsp-bf561 preliminary technical data rev. prc | page 25 of 52 | april 2004 asynchronous memory write cycle timing table 15. asynchronous memory write cycle timing parameter min max unit timing requirements t sardy ardy setup before clkout 4.0 ns t hardy ardy hold after clkout 0.0 ns switching characteristic t ddat data15C0 disable after clkout 6.0 ns t endat data15C0 enable after clkout 1.0 ns t do output delay after clkout 1 6.0 ns t ho output hold after clkout 1 0.8 ns 1 output pins include ams 3C0, abe 3C0, addr25C2, data31C0, aoe, awe . figure 9. asynchronous memory write cycle timing t do t end at clkout amsx abe1?0 be, address t ho write data t ddat data15?0 awe t sardy t hardy setup 2cycles programmed write access 2 cycles access extended 1cycle hold 1cycle ardy addr19?1 t ho t sardy t do
rev. prc | page 26 of 52 | april 2004 adsp-bf561 preliminary technical data sdram interface timing table 16. sdram interface timing parameter min max unit timing requirement t ssdat data setup before clkout 2.1 ns t hsdat data hold after clkout 0.8 ns switching characteristic t sclk clkout period 7.5 ns t sclkh clkout width high 2.5 ns t sclkl clkout width low 2.5 ns t dcad command, addr, data delay after clkout 1 6.0 ns t hcad command, addr, data hold after clkout 1 0.8 ns t dsdat data disable after clkout 6.0 ns t ensdat data enable after clkout 1.0 ns 1 command pins include: sras , scas , swe , sdqm, sms3-0 , sa10, scke. figure 10. sdram interface timing t hcad t hcad t dsdat t dcad t ssdat t dcad t ensdat t hsdat t sclkl t sclkh t sclk clkout data (in) data(out) cmnd addr (out) note: command = sras , scas , swe ,sdqm, sms , sa10, scke.
adsp-bf561 preliminary technical data rev. prc | page 27 of 52 | april 2004 external port bus request and grant cycle timing table 17 and figure 11 describe external port bus request and bus grant operations. table 17. external port bus request and grant cycle timing parameter , 1, 2 min max unit timing requirements t bs br asserted to clkout high setup 4.6 ns t bh clkout high to br de-asserted hold time 0.0 ns switching characteristics t sd clkout low to sms , address, and rd /wr disable 4.5 ns t se clkout low to sms , address, and rd /wr enable 4.5 ns t dbg clkout high to bg asserted setup 3.6 ns t ebg clkout high to bg de-asserted hold time 3.6 ns t dbh clkout high to bgh asserted setup 3.6 ns t ebh clkout high to bgh de-asserted hold time 3.6 ns 1 these are preliminary timing parameters that ar e based on worst-case operating conditions. 2 the pad loads for these timi ng parameters are 20 pf. figure 11. external port bus request and grant cycle timing t bh addr25-2 amsx clkout t bs t sd t sd t sd t dbg t dbh t se t se t se t ebg t ebh bg awe bgh are br abe3-0
rev. prc | page 28 of 52 | april 2004 adsp-bf561 preliminary technical data parallel peripheral interface timing table 18 , figure 12 , describes parallel peripheral interface operations. table 18. parallel peripheral interface timing parameter min max unit timing requirements t pclkw ppix_clk width 1 6.0 ns t pclk ppi_clk period 1 15.0 ns timing requirements t sfspe external frame sync setup before ppi_clk 3.0 ns t hfspe external frame sync h old after ppi_clk 3.0 ns t sdrpe receive data setup before ppi_clk tbd ns t hdrpe receive data hold after ppi_clk tbd ns switching characteristics t dfspe internal frame sync delay after ppi_clk 10.0 ns t hofspe internal frame sync hold after ppi_clk 0.0 ns t ddtpe transmit data delay after ppi_clk 10.0 ns t hdtpe transmit data hold after ppi_clk 0.0 ns 1 ppi_clk frequency cannot exceed f sclk /2 figure 12. timing diagram ppi t ddtpe t hdtpe ppi_clk ppi_fs1 ppix drive edge sample edge t sfspe t hfspe t pclkw t dfspe t hofspe ppi_fs2 t sd rpe t hdrpe
adsp-bf561 preliminary technical data rev. prc | page 29 of 52 | april 2004 serial ports table 19 through table 24 on page 30 and figure 13 on page 31 through figure 15 on page 33 describe serial port operations. table 19. serial portsexternal clock parameter min max unit timing requirements t sfse tfs/rfs setup before tsclk/rsclk 1 3.0 ns t hfse tfs/rfs hold after tsclk/rsclk 1 3.0 ns t sdre receive data setup before rsclk 1 3.0 ns t hdre receive data hold after rsclk 1 3.0 ns t sclkw tsclk/rsclk width 4.5 ns t sclk tsclk/rsclk period 15.0 ns 1 referenced to sample edge. table 20. serial portsinternal clock parameter min max unit timing requirements t sfsi tfs/rfs setup before tsclk/rsclk 1 tbd ns t hfsi tfs/rfs hold after tsclk/rsclk 1 tbd ns t sdri receive data setup before rsclk 1 6.0 ns t hdri receive data hold after rsclk 1 0.0 ns t sclkw tsclk/rsclk width 4.5 ns t sclk tsclk/rsclk period 15.0 ns 1 referenced to sample edge. table 21. serial portsexternal clock parameter min max unit switching characteristics t dfse tfs/rfs delay after tsclk/rsclk (internally generated tfs/rfs) 1 10.0 ns t hofse tfs/rfs hold after tsclk/rsclk (internally generated tfs/rfs) 1 0.0 ns t ddte transmit data delay after tsclk 1 10.0 ns t hdte transmit data hold after tsclk 1 0.0 ns 1 referenced to drive edge.
rev. prc | page 30 of 52 | april 2004 adsp-bf561 preliminary technical data table 22. serial portsinternal clock parameter min max unit switching characteristics t dfs i tfs/rfs delay after tsclk/rsclk (internally generated tfs/rfs) 1 tbd ns t hofs i tfs/rfs hold after tsclk/rsclk (internally generated tfs/rfs) 1 tbd ns t ddt i transmit data delay after tsclk 1 tbd ns t hdt i transmit data hold after tsclk 1 tbd ns t sclkiw tsclk/rsclk width 4.5 ns 1 referenced to drive edge. table 23. serial portsenable and three-state parameter min max unit switching characteristics t dtene data enable delay from external tsclk 1 tbd ns t ddtte data disable delay from external tsclk 1 tbd ns t dteni data enable delay from internal tsclk tbd ns t ddtti data disable delay from internal tsclk 1 tbd ns 1 referenced to drive edge. table 24. external late frame sync parameter min max unit switching characteristics t ddtlfse data delay f rom late e x ternal tfs or ex ternal rfs wit h mce = 1, mfd = 0 1,2 tbd ns t dtenlfse data enable from late fs or mce = 1, mfd = 0 1,2 tbd ns 1 mce = 1, tfs enable and tfs valid follow t ddtenfs and t ddtlfse . 2 if external rfs/tfs setup to rsclk/tsclk > t sclk /2 then t ddtlsck and t dtenlsck apply, otherwise t ddtlfse and t dtenlfs apply.
adsp-bf561 preliminary technical data rev. prc | page 31 of 52 | april 2004 figure 13. serial ports drive edge tclk (int) drive edge tclk/rclk drive edge drive edge tclk/rclk tclk (ext) t ddtte t ddten t ddtti t ddtin dt dt rclk rfs drive edge sample edge data receive? internal clock data receive? external clock rclk rfs drive edge sample edge note: either the rising edge or falling edge of rclk, tclk can be used as the active sampling edge. t sdri t hdri t sfsi t hfsi t dfse t hofse t sclkiw t sdre t hdre t sfse t hfse t dfse t sclkw t hofse dr dr t ddti tclk tfs drive edge sample edge data transmit ? internal clock t sfsi t hfsi t dfsi t hofsi t sclkiw dt t hdti note: either the rising edge or falling edge of rclk or tclk can be used as the active sampling edge. t ddte tclk tfs drive edge sample edge data transmit ? external clock t sfse t hfse t dfse t hofse t sclkw dt t hdte tfs (?late?, ext) tfs (?late?, int)
rev. prc | page 32 of 52 | april 2004 adsp-bf561 preliminary technical data figure 14. external late frame sync (frame sync setup < t sclk/ 2) t ddtlfse t sfse/i t hdte/i rsclk drive drive sample rfs dt 2nd bit 1st bit t ddtenfs t ddte/i t hofse/i t ddtenfs t sfse/i t hdte/i drive drive sample dt tsclk tfs 2nd bit 1st bit t ddtlfse t ddte/i t hofse/i ex t ern a l rf s w i t hm c e=1,mf d = 0 late external tfs
adsp-bf561 preliminary technical data rev. prc | page 33 of 52 | april 2004 figure 15. external late frame sync (frame sync setup > t sclk/ 2) dt rsclk rfs t sfse/i t hofse/i t dtenlsck t ddte/i t hdte/i t ddtlsck drive sample 1st bit 2nd bit drive dt tsclk tfs t sfse/i t hofse/i t dtenlsck t ddte/i t hdte/i t ddtlsck drive sample 1st bit 2nd bit drive late external tfs external rfs with mce=1, mfd=0
rev. prc | page 34 of 52 | april 2004 adsp-bf561 preliminary technical data serial peripheral interface (spi) portmaster timing table 25 and figure 16 describe spi port master operations. table 25. serial peripheral interface (spi) portmaster timing parameter min max unit timing requirements t sspidm data input valid to sck edge (data input setup) tbd ns t hspidm sck sampling edge to data input invalid tbd ns switching characteristics t sdscim spiselx low to first sck edge 2t sclk -1.5 ns t spichm serial clock high period 2t sclk -1.5 ns t spiclm serial clock low period 2t sclk -1.5 ns t spiclk serial clock period 4t sclk -1.5 ns t hdsm last sck edge to spiselx high 2t sclk -1.5 ns t spitdm sequential transfer delay 2t sclk -1.5 ns t ddspidm sck edge to data out valid (data out delay) tbd tbd ns t hdspidm sck edge to data out inva lid (data out hold) tbd tbd ns
adsp-bf561 preliminary technical data rev. prc | page 35 of 52 | april 2004 figure 16. serial peripheral interface (spi) portmaster timing t sspidm t hspidm t hdspidm lsb msb t hspidm t ddspidm mosi (output) miso (input) spiselx (output) sck (cpol = 0) (output) sck (cpol = 1) (output) t spichm t spiclm t spiclm t spiclk t spichm t hdsm t spitdm t hdspidm lsb valid lsb msb msb valid t hspidm t ddspidm mosi (output) miso (input) t sspidm cpha=1 cpha=0 msb valid t sdscim t sspidm lsb valid
rev. prc | page 36 of 52 | april 2004 adsp-bf561 preliminary technical data serial peripheral interfac e (spi) portslave timing table 26 and figure 17 describe spi port slave operations. table 26. serial peripheral interface (spi) portslave timing parameter min max unit timing requirements t spichs serial clock high period 2t sclk -1.5 ns t spicls serial clock low period 2t sclk -1.5 ns t spiclk serial clock period 4t sclk -1.5 ns t hds last sck edge to spiss not asserted 2t sclk -1.5 ns t spitds sequential transfer delay 2t sclk -1.5 ns t sdsci spiss assertion to first sck edge 2t sclk -1.5 ns t sspid data input valid to sck edge (data input setup) 1.6 ns t hspid sck sampling edge to data input invalid 1.6 ns switching characteristics t dsoe spiss assertion to data out active 0 8 ns t dsdhi spiss deassertion to data high impedance 0 8 ns t ddspid sck edge to data out valid (data out delay) 0 10 ns t hdspid sck edge to data out invalid (data out hold) 0 10 ns
adsp-bf561 preliminary technical data rev. prc | page 37 of 52 | april 2004 figure 17. serial peripheral interface (spi) portslave timing t hspid t ddspid t dsdhi lsb msb msb valid t hspid t dsoe t ddspid t hdspid miso (output) mosi (input) t sspid spiss (input) sck (cpol = 0) (input) sck (cpol = 1) (input) t sdsci t spichs t spicls t spicls t spiclk t hds t spichs t sspid t hspid t dsdhi lsb valid msb msb valid t dsoe t ddspid miso (output) mosi (input) t sspid lsb valid lsb cpha=1 cpha=0 t spitds
rev. prc | page 38 of 52 | april 2004 adsp-bf561 preliminary technical data universal asynchronous receiver-transmitter (uart) portreceive and transmit timing figure 18 describes uart port receiv e and transmit operations. the maximum baud rate is sclk/16. as shown in figure 18 there is some latency between the generation internal uart interrupts and the external data operations. these latencies are negligible at the data tran smission rates for the uart. figure 18. uart portreceive and transmit timing rxd data(5?8) internal uart receive interrupt uart receive bit set by data stop; cleared by fifo read clkout (sample clock) txd data(5?8) stop (1?2) internal uart transmit interrupt uart transmit bit set by program; cleared by write to transmit start stop transmit receive as data writen to buffer
adsp-bf561 preliminary technical data rev. prc | page 39 of 52 | april 2004 timer cycle timing table 27 and figure 19 describe timer expired operations. the input signal is asynchronous in width capture mode and external clock mode and has an absolute maximum input fre- quency of f sclk /2 mhz. table 27. timer cycle timing parameter min max unit timing characteristics t wl timer pulsewidth input low 1 1sclk cycles t wh timer pulsewidth input high 1 1sclk cycles switching characteristic t hto timer pulsewidth output 2 1(2 32 C1) sclk cycles 1 the minimum pulsewidths apply for tmrx input pins in width capture and external clock mode s. they also apply to the pf1 or ppic lk input pins in pwm output mode. 2 the minimum time for t hto is one cycle, and the maximum time for t hto equals (2 32 C1) cycles. figure 19. timer pw m_out cycle timing clkout tmrx (pwm output mode) t hto tmrx (width capture and external clock modes) t wl t wh
rev. prc | page 40 of 52 | april 2004 adsp-bf561 preliminary technical data programmable flags cycle timing table 28 and figure 20 describe programmable flag operations. table 28. programmable flags cycle timing parameter min max unit timing requirement t wfi flag input pulsewidth t sclk + 1 ns switching characteristic t dfo flag output delay from clkout low tbd ns figure 20. programmable flags cycle timing flag input pf (input) t wfi pf (output) clkout flag output t dfo
adsp-bf561 preliminary technical data rev. prc | page 41 of 52 | april 2004 jtag test and emulation port timing table 29 and figure 21 describe jtag port operations. table 29. jtag port timing parameter min max unit timing parameters t tck tck period 20 ns t stap tdi, tms setup before tck high 4 ns t htap tdi, tms hold after tck high 4 ns t ssys system inputs setup before tck high 1 4ns t hsys system inputs hold after tck high 1 5ns t trstw trst pulsewidth 2 4tck cycles switching characteristics t dtdo tdo delay from tck low 10 ns t dsys system outputs delay after tck low 3 012ns 1 system inputs=data31-0, ardy, tmr2-0, pf47- 0, ppix_clk, rsclk0-1, rfs0-1, dr0pri, dr 0sec, tsclk0-1, tfs0-1, dr1pri, dr1sec, mos i, miso, sck, rx, reset , nmi, bmode1-0, br , ppixd7-0. 2 50 mhz max. 3 system outputs=data31-0, addr25-2, abe3-0 , aoe , are , awe , ams3-0 , sras , scas , swe , scke, clkout, sa10, sms3-0 , pf47-0, rsclk0-1, rfs0-1, tsclk0- 1, tfs0-1, dt0pri, dt0sec, dt1pri , dt1sec, mosi, miso, sck, tx, bg , bgh , ppixd7-0. figure 21. jtag port timing tms tdi tdo system inputs system outputs tck t tck t htap t stap t dtdo t ssys t hsys t dsys
rev. prc | page 42 of 52 | april 2004 adsp-bf561 preliminary technical data power dissipation total power dissipation has two components, one due to inter- nal circuitry (p int ) and one due to the sw itching of external output drivers (p ext ). table 30 shows the power dissipation for internal circuitry (v ddint ). internal power dissipation is depen- dent on the instruction execution sequence and the data operands involved. the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on ? the number of output pins th at switch during each cycle (o) ? the maximum frequency at which they can switch (f) ? their load capacitance (c) ? their voltage swing (v ddext ) the external component is calculated using: the frequency f includes driving the load high and then back low. for example: data15C0 pins can drive high and low at a maximum rate of 1/(23t sclk ) while in sdram burst mode. a typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation. note that the conditions causing a worst-case p ext differ from those causing a worst-case p int . maximum p int cannot occur while 100% of the output pins are switching from all ones (1s) to all zeros (0s). note also that it is not common for an application to have 100%,or even 50%, of the outputs switching simultaneously. output drive currents figure 22 shows typical i-v characteristics for the output driv- ers of the adsp-bf561. the curv es represent the current drive capability of the output drivers as a function of output voltage. test conditions the ac signal specifications (timing parameters) appear in tim- ing specifications on page 22 . these include output disable time, output enable time, and ca pacitive loading. the timing specifications for the dsp apply for the voltage reference levels in figure 23 . table 30. internal power dissipation test conditions 1 1 i dd data is specified for typical proc ess parameters. all data at 25oc. parameter f cclk = 50 mhz v ddint = 0.8 v f cclk = 400 mhz v ddint = 1.2 v f cclk = 600 mhz v ddint = 1.2 v f cclk = 600 mhz v ddint = 1.35 v unit i ddtyp 2 2 processor executing 75% dual mac, 25% add with moderate data bus activity. tbd tbd 520 tbd ma i ddsleep 3 3 see the adsp-bf53x blackfin proce ssor hardware reference manual for definitions of sleep and deep sleep operating modes. tbd tbd tbd tbd ma i dddeepsleep 3 tbd tbd 70 tbd ma i ddhi- bernate 4 4 measured at v ddext = 3.65v with voltage regulator off (v ddint = 0v). tbd tbd tbd tbd a figure 22. adsp-bf561 typical drive p ext oc v 2 dd f = p total p ext i dd v ddint () + = source (vddext) voltage - v 120 -20 -80 03.5 0.5 1 1.5 2 2.5 3 100 0 -40 -60 60 20 80 40 -100 -120 s o u r c e ( v d d e x t ) c u r r e n t - m a t b d figure 23. voltage reference levels for ac measurements (except output enable/disable) input or output 1.5v 1.5v
adsp-bf561 preliminary technical data rev. prc | page 43 of 52 | april 2004 output enable time output pins are considered to be enabled when they have made a transition from a high impedanc e state to the point when they start driving. the output enable time t ena is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output starts driving as shown in the output enable/disable diagram ( figure 24 ). the time t ena_measured is the interval from when the reference signal switches to when the output vo ltage reaches 2.0v (output high) or 1.0v (output low). time t trip is the interval from when the output starts driving to when the output reaches the 1.0v or 2.0v trip voltage. time t ena is calculated as t ena_measured Ct trip . if multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. output disable time output pins are considered to be disabled when they stop driv- ing, go into a high impedance stat e, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by v is dependent on the capacitive load, c l and the load current, i l . this decay time can be approximated by the following equation: the output disable time t dis is the difference between t dis_measured and t decay as shown in figure 24 .the time t dis_measured is the interval from when the reference signal switches to when the output voltage decays v from the mea- sured output high or output low voltage. t decay is calculated with test loads c l and i l , and with v equal to 0.5 v. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation given above. choose v to be the difference between the adsp-bf561's output volt- age and the input threshold for the device requiring the hold time. a typical v will be 0.4 v. cl is the total bus capacitance (per data line), and il is the total leakage or three-state current (per data line). the hold time will be t decay plus the minimum disable time (i.e., t dsdat for an sdram write cycle). figure 24. output enable/disable t decay c l v ? () i l ? = reference signal t dis output starts driving v oh (measured) - v v ol (measured) + v t dis-measured v oh (measured) v ol (measured) 2.0v 1.0v v oh (measured) v ol (measured) high-impedance state. test conditions cause this voltage to be approximately 1.5v. output stops driving t ena t decay t ena-measured t trip figure 25. typical output delay or hold vs. load capacitance (at max case temperature) load capacitance - pf 5 -5 0210 30 60 90 120 150 180 4 3 2 1 nominal o u t p u t d e l a y o r h o l d - n s t b d
rev. prc | page 44 of 52 | april 2004 adsp-bf561 preliminary technical data capacitive loading output delays and holds are based on standard capa citive loads: 30 pf on all pins (see figure 26 on page 44 ). figure 25 shows graphically how output delays an d holds vary with load capaci- tance (note that this graph or de rating does not apply to output disable delays; see output disable time on page 43 ). the graphs of figure 25 , figure 27 and figure 28 may not be linear outside the ranges shown, for typical output delay vs. load capaci- tance and typical output rise time (10%-90%, v=min) vs. load capacitance. figure 26. equivalent device loading for ac measurements (includes all fixtures) figure 27. typical output rise/fall time (10%-90%, vddext = max) 1.5v 20pf to output pin 50 v load capacitance - pf 16.0 8.0 0 0200 20 40 60 80 100 120 140 160 180 14.0 12.0 4.0 2.0 10.0 6.0 r i s e a n d f a l l t i m e s - n s ( . v - v , 2 0 % - 8 0 % ) t b d figure 28. typical output rise/fall time (10%-90%, vddext = min) load capacitance - pf 2.0 0 0200 20 40 60 80 100 120 140 160 180 3.5 3.0 1.0 0.5 2.5 1.5 r i s e a n d f a l l t i m e s - n s ( 0 . v - v , 2 0 % - 8 0 % ) t b d
adsp-bf561 preliminary technical data rev. prc | page 45 of 52 | april 2004 256-ball mbga pin configurations table 31. 256-lead mbga pin assignments mbga pin no. pin name mbga pin no. pin name mbga pin no. pin name mbga pin no. pin name a01 vddext b01 ppi2clk c01 ppi1sync2/tmr9 d01 ppi1d13/pf45 a02 addr24 b02 addr22 c02 ppi1clk d02 ppi1d15/pf47 a03 addr20 b03 addr18 c03 addr25 d03 ppi1sync3 a04 vddext b04 addr16 c04 addr19 d04 addr23 a05 addr14 b05 addr12 c05 gnd d05 gnd a06 addr10 b06 vddext c06 addr11 d06 gnd a07 ams3 b07 ams1 c07 aoe d07 addr09 a08 awe b08 are c08 ams0 d08 gnd a09 vddext b09 sms1 c09 sms2 d09 ardy a10 sms3 b10 scke c10 sras d10 scas a11 sclk0/clkout b11 vddext c11 gnd d11 sa10 a12 sclk1 b12 br c12 bgh d12 vddext a13 bg b13 abe1 /sdqm1 c13 gnd d13 addr02 a14 abe2 /sdqm2 b14 addr06 c14 addr07 d14 gnd a15 abe3 /sdqm3 b15 addr04 c15 data1 d15 data5 a16 vddext b16 data0 c16 data3 d16 data6 e01 gnd f01 clkin g01 xtal h01 gnd e02 ppi1d11/pf43 f02 vddext g02 gnd h02 gnd e03 ppi1d12/pf44 f03 reset g03 vddext h03 ppi1d9/pf41 e04 ppi1sync1/tmr8 f04 ppi1d10/pf42 g04 bypass h04 ppi1d7 e05 addr15 f05 addr21 g05 ppi1d14/pf46 h05 ppi1d5 e06 addr13 f06 addr17 g06 gnd h06 vddint e07 ams2 f07 vddint g07 gnd h07 vddint e08 vddint f08 gnd g08 gnd h08 gnd e09 sms0 f09 vddint g09 vddint h09 gnd e10 swe f10 gnd g10 addr05 h10 gnd e11 abe0 /sdqm0 f11 addr08 g11 addr03 h11 vddint e12 data2 f12 data10 g12 data15 h12 data16 e13 gnd f13 data8 g13 data14 h13 data18 e14 data4 f14 data12 g14 gnd h14 data20 e15 data7 f15 data9 g15 data13 h15 data17 e16 vddext f16 data11 g16 vddext h16 data19
rev. prc | page 46 of 52 | april 2004 adsp-bf561 preliminary technical data j01 vrout0 k01 ppi1d6 l01 ppi1d0 m01 ppi2d15/pf39 j02 vrout1 k02 ppi1d4 l02 ppi2sync2/tmr11 m02 ppi2d13/pf37 j03 ppi1d2 k03 ppi1d8/pf40 l03 gnd m03 ppi2d9/pf33 j04 ppi1d3 k04 ppi2sync1/tmr10 l04 ppi2sync3 m04 gnd j05 ppi1d1 k05 ppi2d14/pf38 l05 vddext m05 nc j06 vddext k06 vddext l06 ppi2d11/pf35 m06 pf3/spisel3/tmr3 j07 gnd k07 gnd l07 gnd m07 pf7/spisel7/tmr7 j08 vddint k08 vddint l08 vddint m08 vddint j09 vddint k09 gnd l09 gnd m09 gnd j10 vddint k10 gnd l10 vddext m10 bmode0 j11 gnd k11 vddint l11 gnd m11 sck j12 data30 k12 data28 l12 dr0pri m12 dr1pri j13 data22 k13 data26 l13 tfs0/pf16 m13 nc j14 gnd k14 data24 l14 gnd m14 vddext j15 data21 k15 data25 l15 data27 m15 data31 j16 data23 k16 vddext l16 data29 m16 dt0pri/pf18 n01 ppi2d12/pf36 p01 ppi2d8/pf32 r01 ppi2d7 t01 vddext n02 ppi2d10/pf34 p02 gnd r02 ppi2d6 t02 ppi2d4 n03 ppi2d3 p03 ppi2d5 r03 ppi2d2 t03 vddext n04 ppi2d1 p04 pf0/spiss/tmr0 r04 ppi2d0 t04 pf2/spisel2/tmr2 n05 pf1/spisel1/tmr1 p05 gnd r05 pf4/spisel4/tmr4 t05 pf6/spisel6/tmr6 n06 pf9 p06 pf5/spisel5/tmr5 r06 pf8 t06 vddext n07 gnd p07 pf11 r07 pf10 t07 pf12 n08 pf13 p08 pf15/extclk r08 pf14 t08 vddext n09 tdo p09 gnd r09 nmi1 t09 tck n10 bmode1 p10 t r st r10 tdi t10 tms n11 mosi p11 nmi0 r11 br t11 sleep n12 gnd p12 gnd r12 miso t12 vddext n13 rfs1/pf24 p13 rsclk1/pf30 r13 tx/pf26 t13 rx/pf27 n14 gnd p14 tfs1/pf21 r14 tsclk1/pf31 t14 dr1sec/pf25 n15 dt0sec/pf17 p15 rsclk0/pf28 r15 dt1pri/pf23 t15 dt1sec/pf22 n16 tsclk0/pf29 p16 dr0sec/pf20 r16 rfs0/pf19 t16 vddext table 31. 256-lead mbga pin assignments (continued) mbga pin no. pin name mbga pin no. pin name mbga pin no. pin name mbga pin no. pin name
adsp-bf561 preliminary technical data rev. prc | page 47 of 52 | april 2004 297-ball pbga pin configurations table 32. 297-lead pbga pin assignments mbga pin no. pin name mbga pin no. pin name mbga pin no. pin name mbga pin no. pin name a01 gnd ab03 gnd ae11 pf12 af17 sleep a02 addr25 ab24 gnd ae12 pf14 af18 nmi0 a03 addr23 ab25 tfs0/pf16 ae13 nc af19 sck a04 addr21 ab26 dr0pri ae14 tdo af20 tx/pf26 a05 addr19 ac01 ppi2d9/pf33 ae15 trst af21 rsclk1/pf30 a06 addr17 ac02 ppi2d8/pf32 ae16 emu af22 dr1pri a07 addr15 ac03 gnd ae17 bmode1 af23 tsclk1/pf31 a08 addr13 ac04 gnd ae18 bmode0 af24 dt1sec/pf22 a09 addr11 ac23 gnd ae19 miso af25 dt1pri/pf23 a10 addr09 ac24 gnd ae20 mosi af26 gnd a11 ams3 ac25 dr0sec/pf20 ae21 rx/pf27 b01 ppi2clk a12 ams1 ac26 rfs0/pf19 ae22 rfs1/pf24 b02 gnd a13 awe ad01 ppi2d7 ae23 dr1sec/pf25 b03 addr24 a14 are ad02 ppi2d6 ae24 tfs1/pf21 b04 addr22 a15 sms0 ad03 gnd ae25 gnd b05 addr20 a16 sms2 ad04 gnd ae26 nc b06 addr18 a17 sras ad05 gnd af01 gnd b07 addr16 a18 scas ad22 gnd af02 ppi2d4 b08 addr14 a19 sclk0/clkout ad23 gnd af03 ppi2d2 b09 addr12 a20 sclk1 ad24 gnd af04 ppi2d0 b10 addr10 a21 bgh ad25 nc af05 pf1/spisel1/tmr1 b11 ams2 a22 abe0 /sdqm0 ad26 rsclk0/pf28 af0 6 pf3/spisel3/tmr3 b12 ams0 a23 abe2 /sdqm2 ae01 ppi2d5 af07 pf5/spisel5/tmr5 b13 aoe a24 addr08 ae02 gnd af08 pf7/spisel7/tmr7 b14 ardy a25 addr06 ae03 ppi2d3 af09 pf9 b15 sms1 a26 gnd ae04 ppi2d1 af10 pf11 b16 sms3 aa01 ppi2d13/pf37 ae05 pf0/spiss/tmr0 af11 pf13 b17 scke aa02 ppi2d12/pf36 ae06 pf2/spisel2/tmr2 af12 pf15/ext clk b18 swe aa25 dt0sec/pf17 ae07 pf4/spisel4/tmr4 af13 nmi1 b19 sa10 aa26 tsclk0/pf29 ae08 pf6/spisel6/tmr6 af14 tck b20 br ab01 ppi2d11/pf35 ae09 pf8 af15 tdi b21 bg ab02 ppi2d10/pf34 ae10 pf10 af16 tms b22 abe1 /sdqm1
rev. prc | page 48 of 52 | april 2004 adsp-bf561 preliminary technical data b23 abe3 /sdqm3 g01 ppi1d11/pf43 k25 data10 n12 gnd b24 addr07 g02 ppi1d10/pf42 k26 data13 n13 gnd b25 gnd g25 data4 l01 nc n14 gnd b26 addr05 g26 data7 l02 nc n15 gnd c01 ppi1sync3 h01 bypass l10 vddext n16 gnd c02 ppi1clk h02 reset l11 gnd n17 gnd c03 gnd h25 data6 l12 gnd n18 vddint c04 gnd h26 data9 l13 gnd n25 data16 c05 gnd j01 clkin l14 gnd n26 data19 c22 gnd j02 gnd l15 gnd p01 ppi1d7 c23 gnd j10 vddext l16 gnd p02 ppi1d8/pf40 c24 gnd j11 vddext l17 gnd p10 vddext c25 addr04 j12 vddext l18 vddint p11 gnd c26 addr03 j13 vddext l25 data12 p12 gnd d01 ppi1sync1/tmr8 j14 vddext l26 data15 p13 gnd d02 ppi1sync2/tmr9 j15 vddext m01 vrout0 p14 gnd d03 gnd j16 vddint m02 gnd p15 gnd d04 gnd j17 vddint m10 vddext p16 gnd d23 gnd j18 vddint m11 gnd p17 gnd d24 gnd j25 data8 m12 gnd p18 vddint d25 addr02 j26 data11 m13 gnd p25 data18 d26 data1 k01 xtal m14 gnd p26 data21 e01 ppi1d15/pf47 k02 nc m15 gnd r01 ppi1d5 e02 ppi1d14/pf46 k10 vddext m16 gnd r02 ppi1d6 e03 gnd k11 vddext m17 gnd r10 vddext e24 gnd k12 vddext m18 vddint r11 gnd e25 data0 k13 vddext m25 data14 r12 gnd e26 data3 k14 vddext m26 data17 r13 gnd f01 ppi1d13/pf45 k15 vddext n01 vrout1 r14 gnd f02 ppi1d12/pf44 k16 vddint n02 ppi1d9/pf41 r15 gnd f25 data2 k17 vddint n10 vddext r16 gnd f26 data5 k18 vddint n11 gnd r17 gnd table 32. 297-lead pbga pin assignments (continued) mbga pin no. pin name mbga pin no. pin name mbga pin no. pin name mbga pin no. pin name
adsp-bf561 preliminary technical data rev. prc | page 49 of 52 | april 2004 r18 vddint t16 gnd u14 gnd w01 ppi2sync1/tmr10 r25 data20 t17 gnd u15 vddint w02 ppi2sync2/tmr11 r26 data23 t18 vddint u16 vddint w25 data28 t01 ppi1d3 t25 data22 u17 vddint w26 data31 t02 ppi1d4 t26 data25 u18 vddint y01 ppi2d15/pf39 t10 vddext u01 ppi1d1 u25 data24 y02 ppi2d14/pf38 t11 gnd u02 ppi1d2 u26 data27 y25 data30 t12 gnd u10 vddext v01 ppi2sync3 y26 dt0pri/pf18 t13 gnd u11 vddext v02 ppi1d0 t14 gnd u12 vddext v25 data26 t15 gnd u13 vddext v26 data29 table 32. 297-lead pbga pin assignments (continued) mbga pin no. pin name mbga pin no. pin name mbga pin no. pin name mbga pin no. pin name
rev. prc | page 50 of 52 | april 2004 adsp-bf561 preliminary technical data outline dimensions dimensions in the outline dimension figure are shown in millimeters. figure 29. 256-ball mini-ball grid array a cl cl 0.65 bsc ball pitch 9.75 bsc sq top view a1 ball pad corner 12.00 bsc sq notes 1. dimensions are in millimeters. 2. complies with jedec registered outline mo-225, with no exact package size and exception to package height. 3. minimum ball height 0.25 side view detail a 1.70 1.51 1.36 detail a seating plane 0.45 0.40 0.35 ball diameter 0.10 max coplanarity 0.25 min bottom view a1 ball pad corner m b c d e f g h j k l n p r t a 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 256-ball mini bga (bc-256)
adsp-bf561 preliminary technical data rev. prc | page 51 of 52 | april 2004 outline dimensions dimensions in the outline dimension figure are shown in millimeters. ordering guide figure 30. 297-ball pbga grid array part number ambient temperature range instruction rate operating voltage adsp-bf561skbcz600 0oc to +70oc 600 mhz 0.8 v to 1.2 v internal, 2.5 v or 3.3 v i/o adsp-bf561skbcz500 0oc to +70oc 500 mhz 0.8 v to 1.2 v internal, 2.5 v or 3.3 v i/o ADSP-BF561SBB500 -40oc to +85oc 500 mhz 0.8 v to 1.2 v internal, 2.5 v or 3.3 v i/o a 8 .00 8 .00 cl cl 1.00 bsc ball pitch 25.00 bsc sq top view a1 ball pad corner 27.00 bsc sq notes 1. dimensions are in millimeters. 2. complies with jedec registered outline ms-034, variation aal-1. 3. minimum ball height 0.40 side view detail a 2.43 2.23 2.03 detail a seating plane 0.70 0.60 0.50 ball diameter 0.20 max coplanarity 0.40 min bottom view a1 ball pad corner m b c d e f g h j k l n p r t u v w y aa ab ac ad ae af a 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 8 19 20 21 22 23 24 25 26 1 2 297-ball pbga (b-297)
rev. prc | page 52 of 52 | april 2004 adsp-bf561 preliminary technical data

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